4-10 years’ experience in verification domain
- Participate in verification environment and test plan development of Application Specific Processor, IP and SOCs.
- Involve in test bench development, test case coding and execution.
- Involve in gate level simulation, power aware simulation and behavior model development.
- Debug of failing test cases, regression debug, coverage analysis and coverage closure.
- Good knowledge of digital logic design basics.
- Good knowledge of Verification architecture, test plan. development and coverage analysis.
- Strong in System Verilog, Verilog & C programming.
- Good knowledge in gate-level simulation, and Scripting languages like Perl, TCL.
- Very good debugging and analytical skills.
- Demonstrated ability to deliver with minimum guidance.
- Knowledge of power aware simulation and Application Specific Processor verification is a plus.