- 10 years or more with proven ability to deliver assignments
- Past exposure to Wireless IP, CPU Architecture, and DSP Concepts is a plus.
- BE / M.Tech in Electronics / Communication / Telecommunications.
- Verification Bench definition and Test plan creation for complex IP’s
- Ability to understand IP functionality in order to create a comprehensive test plan.
- Verification strategy definition using verification concepts like UVM etc.
- Implementation of Verification Bench and development of test cases on the same.
- Good understanding of Verification Coverage and Coverage-driven closure.
- Debugging of verification and regression failures, working with RTL team member(s) to quickly resolve the same.
- Gate-level simulation.
- Low power simulation using UPF.
- Monitoring and guidance of junior team members.
- Planning and tracking of verification activities. Ability to deliver as a team on schedule with maximum verification coverage.
- Ability to take complete ownership of the verification of major IP modules or SoC sub-systems.
- Strong background in digital design concepts.
- Strong in System Verilog, Verilog & C programming.
- Knowledge of UVM Methodology, Assertions, Formal Verification Methods etc.
- Very good debugging and analytical skills.
- Coordination skills with other teams and colleagues.