LOCATION: Bangalore


  • Up to 15 years
  • Past exposure to Wireless IP, CPU Architecture, and DSP Concepts is a plus.


  • Must be B. E/ B. S/ B. Tech/ M.S/ME/MTech in EC/EE/CS (Related branches will be considered)
  • Strong academic background with excellent oral and written communication


  • Verification Bench definition and Test plan creation for complex IP’s
    • Ability to understand IP functionality to create a comprehensive test plan.
    • Verification strategy definition using verification concepts like UVM etc.
  • SoC-level/Top-level Verification
    • Define SoC-level verification strategies after getting a good understanding of SoC functionality.
    • Define and execute test cases to achieve maximum SoC-level coverage with the minimum development effort.
    • Experience in a C-based environment with multi-processors, with test development in C language.
  • Implementation of Verification Infrastructure and development of test cases on the same.
  • Good understanding of Verification Coverage and Coverage-driven closure.
  • Debugging of verification and regression failures, working with RTL team member(s) to quickly resolve the same.
  • Gate-level & post-route simulation.
  • Low power simulation using UPF.


  • Strong background in digital design concepts.
  • Strong in System Verilog, Verilog & C programming.
  • Knowledge of UVM Methodology, Assertions, Formal Verification, etc.
  • Very good debugging and analytical skills.
  • Hands-on experience in lab debugging is a plus.
  • Good coordination with other teams and colleagues.

Other responsibilities include

  • Monitoring and guidance of junior team members.
  • Planning and tracking of verification activities. Ability to deliver as a team on schedule with maximum verification coverage.
  • Ability to take complete ownership of the verification of major IP modules or SoC sub-systems.