LOCATION: Bangalore


  • Up to 15 years
  • Past exposure to Wireless IP, CPU Architecture, and DSP Concepts is a plus.


  • Must be B. E/ B. S/ B. Tech/ M.S/ME/MTech in EC/EE/CS (Related branches will be considered)
  • Strong academic background with excellent oral and written communication


  • Microarchitecture for different kinds of Digital IP modules targeted towards IC or FPGA.
    • Definition of IP features and interfaces.
    • Partitioning of overall requirements into functional modules for optimum implementation.
    • Good HW-SW partitioning wherever needed.
    • Detailed design of digital logic, FSMs, Pipelines, Bus Interfaces, Register Specifications, etc.
    • Interaction with other functions like SW or Algorithm teams to refine the definition.
  • Implementation
    • Good documentation of the microarchitecture, user guide, design details, etc.
    • RTL coding, sanity testing, and Lint.
    • Support to verification team.
    • Post-RTL activities like Synthesis, Timing Closure, Formal Verification, ECOs, etc.
    • Knowledge of power-aware design concepts like UVM, DVFS, etc.
  • SoC integration and related activities
    • Integration of external as well as internal IP’s.
    • Understanding of aspects like DFT, testability, and integration of analog modules.
    • Verification support.
  • Support for lab debug & troubleshooting on a need basis.


  • Strong digital design and architecture skills.
  • Proven track record in delivering IP modules and/or SoC designs.
  • Strong analytical and problem-solving skills.
  • Good coordination skills with other team members or functions.

For Lead role

  • Ability to take complete ownership of major IP modules or SoC sub-systems with the support of junior members.
  • Ability to deliver as a team on schedule with the required quality.
  • Mentoring and guidance of junior team members.
  • Task planning and tracking of the same.